1. Field of the Invention
This invention relates to a shift register type memory device consisting of a plurality of memory chips.
2. Description of the Prior Art
The technique wherein dummy minor loops are disposed in a magnetic bubble memory device employing the major-minor organization and wherein in the case of the presence of a defect minor loop, the dummy loop is used in place thereof, has been already described in U.S. Pat. No. 3,792,450 and U.S. Patent Application Ser. No. 675,338 now U.S. Pat. No. 4,125,875. In the former patent, the positions of defect loops are stored by arraying "1" and "0" in the order of minor loops in correspondence with good and defective loops. In the latter patent, the defective loop positions are coded into binary numbers and are stored. The latter patent has a shorter access time.
For the purposes of eliminating noises and enhancing the transfer speed, two chips are usually connected to a single sense amplifier, and data written into the chips is read out alternately from the two chips one by one. That is, data at even bit position is read out from the first chip, and data at odd bit positions from the second chip. Signals thus obtained are added up by the amplifier, converted into unipolar pulses by a rectifier, and converted into digital signals by a discriminator.
When both the two chips are non-defective, output signals at correct bit positions are obtained.
However, when either of the chips has a defect, the situation becomes different. Assume that a minor loop for providing data at bit position No. 4 of the first chip is defective. When the data is entered into the next minor loop, the data appears at bit position No. 6, and data at bit position No. 6 appears at No. 8.
In order to solve such a problem, there has been adopted a measure wherein data pulse trains from the respective chips are made separate and independent, pulse train rearrangement circuits are disposed for the respective pulse trains, and lastly, the two pulse trains corrected by the circuits are added.
Such a dummy loop control system has the disadvantage that a pulse train rearrangement circuit is required for each chip. Thus, a large number of pulse train rearrangement circuits are required in a large-capacity memory device employing many chips, resulting in a tremendous cost.